An inverter circuit is customarily used as a circuit for driving a load such as a fluorescent lamp and a motor. FIG. 12 is a circuit diagram showing a schematic structure of an inverter circuit. In this inverter circuit, switching devices such as high-insulation MOSFETs 23, 24 are connected to a power source line which has a high potential (e.g., 100 to 700 V). An output to a load 25 is supplied from a junction 26 between the two high-insulation MOSFETs 23, 24.
A driving circuit 27 which drives the two high-insulation MOSFETs 23, 24 divides an input signal which is supplied from outside (denoted as "EXTERNAL SIGNAL" in FIG. 12) into a high-voltage circuit portion 28 (which operates with a power source potential of 120 V to 720 V, for example, while a reference potential is usually 100 to 700 V) and a low-voltage circuit portion 29 (which operates with a power source potential of 20 V or lower, for example), so that gates of the respective high-insulation MOSFETs 23, 24 are provided with signals. The driving circuit 27, in many cases, is an integrated circuit in which the high-voltage circuit portion 28 and the low-voltage circuit portion 29 are formed in the same semiconductor chip.
FIG. 13 is a schematic cross sectional view showing a cross sectional structure of a conventional integrated circuit. FIG. 13 omits circuit elements which are formed inside the integrated circuit. A major characteristic of the conventional structure is that an N.sup.- - epitaxial layer 31 is formed on a P.sup.- - semiconductor substrate 30 and that a P.sup.+ - region 32 which has a high concentration and separates the N.sup.- - epitaxial layer 31 is formed by diffusion for the purpose of isolating a high voltage circuit and a low voltage circuit from each other (i.e., a PN isolation). The N.sup.- - epitaxial layer 31 is isolated as the P.sup.- - semiconductor substrate 30 and the P.sup.+ - region 32 are grounded, whereby a high-voltage circuit portion A (not shown) and a low-voltage circuit portion B (not shown) are formed respectively in the P.sup.- - semiconductor substrate 30 and the P.sup.+ - region 32. Denoted at 33 is a protective film which is formed in a surface of the P.sup.- - semiconductor substrate 30. Elements which constitute the high-voltage circuit portion A and the low-voltage circuit portion B which are not shown are formed by bipolar transistors or MOSFETs.
In such an integrated circuit using the P.sup.- - semiconductor substrate 30, as a voltage for using the integrated circuit is higher, the N.sup.- - epitaxial layer 31 needs be thicker. FIG. 14 shows a cross sectional structure of an integrated circuit which is disclosed in Japanese Patent Application Laid-Open Gazette No. 4-180249 (Applicant: Mitsubishi Electric Corporation), for example. In this integrated circuit, an N.sup.- - epitaxial layer 31 is formed in a P.sup.- - semiconductor substrate 30, and after forming an N- buried layer 35 which serves as a collector of a bipolar transistor in the N.sup.- - epitaxial layer 31, a second N.sup.- - epitaxial layer 34 is formed over the N.sup.- - epitaxial layer 31 to thereby form a P.sup.+ - layer 32 which acts as an isolation region, and circuit elements are formed in the thick N.sup.- - epitaxial layers 31, 34. Denoted at 36 is a base region, denoted at 37 is an emitter region, demoted at 38 is a collector wall region, and denoted at 39 is an electrode.
As shown in the examples in FIGS. 13 and 14, in general, a conventional high-insulation integrated circuit comprising a high-voltage circuit portion is manufactured using the P.sup.- - semiconductor substrate 30 which includes the thick N.sup.- - epitaxial layers 31, 34. In this case, fabrication of the substrate requires a number of manufacturing processes and a long processing time, which is disadvantageous in terms of manufacturing costs.
In addition, even if the N.sup.- - epitaxial layers 31, 34 are formed thick, a breakdown voltage in the isolation is at most about 200 V, which can not allow a use for driving a high-insulation transistor to which a higher voltage of a few hundreds volts or higher, for instance, is applied.
Further, as the N.sup.- - epitaxial layers 31, 34 become thicker, the P.sup.+ - layer 32 for element isolation needs to have a high concentration so as to be diffused deeper. However, a high concentration of the P.sup.+ - layer 32 reduces an insulation breakdown voltage between the P.sup.+ - layer 32 and the N.sup.- - epitaxial layers 31, 34.
Moreover, since the P.sup.+ - layer 32 is diffused largely not only in the direction of the depth but in a lateral direction as well, the surface area size of the isolation region becomes large relative to the surface area size of a chip as a whole, which is disadvantageous to integration.
For the reasons described above, an apparatus which does not use the N.sup.- - epitaxial layers 31, 34 and a PN isolation is more desirable, with respect to manufacturing costs, a higher breakdown voltage of a produce and a higher integration of the circuit portions.